Optimized Implementation of a Feature Detector for Embedded Systems Based on the Accelerated Segment Test

Abstract

Recent developments made portable embedded systems cheaper, even smaller, and also enormously increased their computing power. But performance in a system itself cannot only be gained by using faster and better hardware or simply utilizing multiple general purpose processor cores, it can also be enhanced by adaption for special auxiliary hardware and optimization of time-critical software parts. Especially when large amounts of data have to be processed, as in image processing algorithms, the benefits of parallel data processing can exceed the additional optimization effort. This thesis will show how to take advantage of the additional processing power of the TI DM3730 processor in the use case of a feature detector based on the Accelerated Segment Test. Two ways of unburdening the CPU by using either SIMD extensions on the CPU itself or by transferring the task to the on-chip DSP were implemented and validated. The evaluation of several ideas and possibilities for optimizations led to the final implementations that reduced processing times by more than 25% on both units.