elib
DLR-Header
DLR-Logo -> http://www.dlr.de
DLR Portal Home | Imprint | Privacy Policy | Contact | Deutsch
Fontsize: [-] Text [+]

Optimized Implementation of a Feature Detector for Embedded Systems Based on the Accelerated Segment Test

Fink, Peter (2014) Optimized Implementation of a Feature Detector for Embedded Systems Based on the Accelerated Segment Test. Bachelor's. DLR-Interner Bericht. DLR-IB-RM-OP-2014-3, 52 S.

[img] PDF
3MB

Abstract

Recent developments made portable embedded systems cheaper, even smaller, and also enormously increased their computing power. But performance in a system itself cannot only be gained by using faster and better hardware or simply utilizing multiple general purpose processor cores, it can also be enhanced by adaption for special auxiliary hardware and optimization of time-critical software parts. Especially when large amounts of data have to be processed, as in image processing algorithms, the benefits of parallel data processing can exceed the additional optimization effort. This thesis will show how to take advantage of the additional processing power of the TI DM3730 processor in the use case of a feature detector based on the Accelerated Segment Test. Two ways of unburdening the CPU by using either SIMD extensions on the CPU itself or by transferring the task to the on-chip DSP were implemented and validated. The evaluation of several ideas and possibilities for optimizations led to the final implementations that reduced processing times by more than 25% on both units.

Item URL in elib:https://elib.dlr.de/113188/
Document Type:Monograph (DLR-Interner Bericht, Bachelor's)
Title:Optimized Implementation of a Feature Detector for Embedded Systems Based on the Accelerated Segment Test
Authors:
AuthorsInstitution or Email of AuthorsAuthors ORCID iD
Fink, PeterUNSPECIFIEDUNSPECIFIED
Date:17 April 2014
Refereed publication:No
Open Access:Yes
Gold Open Access:No
In SCOPUS:No
In ISI Web of Science:No
Number of Pages:52
Status:Published
Keywords:DSP, CPU, Co-processor, Image processing, Embedded system, AST, Accelerated Segment Test, SIMD
Institution:HS Augsburg
Department:Fakultät für Informatik
HGF - Research field:Aeronautics, Space and Transport
HGF - Program:Space
HGF - Program Themes:Space Technology
DLR - Research area:Raumfahrt
DLR - Program:R SY - Technik für Raumfahrtsysteme
DLR - Research theme (Project):R - Vorhaben Multisensorielle Weltmodellierung
Location: Oberpfaffenhofen
Institutes and Institutions:Institute of Robotics and Mechatronics (since 2013) > Autonomy and Teleoperation
Institute of Robotics and Mechatronics (since 2013)
Deposited By: Lutz, Philipp
Deposited On:02 Aug 2017 14:16
Last Modified:31 Jul 2019 20:10

Repository Staff Only: item control page

Browse
Search
Help & Contact
Information
electronic library is running on EPrints 3.3.12
Copyright © 2008-2017 German Aerospace Center (DLR). All rights reserved.