FPGA Implementation of a Scalable SAR Image Processor for CFAR Object Detection

Kurzfassung

Ship detection on satellite SAR imagery regularly relies on CFAR algorithms for bright pixel discrimination. However, these algorithms are computationally complex, resulting in long processing times especially for high-resolution images, which is in conflict with the time-criticality of ship detection products. To satisfy the requirement of high product resolution and rapid delivery, an FPGA-based implementation of cell-averaging CFAR is presented. For the first time, High Bandwidth Memory is employed to eliminate previous memory bottlenecks and make full use of a pipelined datapath. Processing of a full Sentinel-1 IW high-resolution scene finishes in less than 8 seconds, while even higher resolution products such as TerraSAR-X StripMap are supported as well and processed in under 15 seconds. At the same time, power efficiency improves by an order of magnitude compared to a conventional server-grade CPU.