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Timing instructions for RISC-V based hard real time edge devices

Ravani Nanjundaswamy, Nithin and Grüttner, Kim (2022) Timing instructions for RISC-V based hard real time edge devices. 5th Workshop on RISC-V Activities, 2022-11-07, Berlin, Germany.

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For real-time systems, the temporal behavior of software is as important as its logical behavior. Ensuring correct temporal behavior at runtime becomes challenging as the complexity of the system increases. A main reason for this is the measurement and control of timing spans all abstraction layers in computing, including programming languages, memory hierarchy, pipelining techniques, bus architectures, memory management and task scheduling. The majority of software solutions to temporal requirements rely on programmable timers/interrupts which adds additional overhead to the system. RISC-V provides an open and extendable ISA (Instruction Set Architecture) enabling a new era of innovation in processor customization and performance and power optimization. This work presents a new RISC-V ISA extension to obtain high-precision cycle-accurate temporal behavior of real-time systems with low overhead. The work proposes a programming model supported by a new custom instruction that measures and controls the execution time of real-time software. The proposed custom instruction-based timing extension is evaluated against a pure software solution with a traditional timer/interrupt solution with respect to the resulting instruction density vs. hardware area overhead.

Item URL in elib:https://elib.dlr.de/194608/
Document Type:Conference or Workshop Item (Speech, Poster)
Title:Timing instructions for RISC-V based hard real time edge devices
AuthorsInstitution or Email of AuthorsAuthor's ORCID iDORCID Put Code
Ravani Nanjundaswamy, NithinUNSPECIFIEDhttps://orcid.org/0009-0008-4739-2378134644668
Grüttner, KimUNSPECIFIEDhttps://orcid.org/0000-0002-4988-3858UNSPECIFIED
Date:7 November 2022
Refereed publication:No
Open Access:Yes
Gold Open Access:No
In ISI Web of Science:No
Keywords:RISC-V ISA extension, Time monitoring
Event Title:5th Workshop on RISC-V Activities
Event Location:Berlin, Germany
Event Type:Workshop
Event Date:7 November 2022
HGF - Research field:Aeronautics, Space and Transport
HGF - Program:Transport
HGF - Program Themes:Road Transport
DLR - Research area:Transport
DLR - Program:V ST Straßenverkehr
DLR - Research theme (Project):V - V&V4NGC - Methoden, Prozesse und Werkzeugketten für die Validierung & Verifikation von NGC
Location: Oldenburg
Institutes and Institutions:Institute of Systems Engineering for Future Mobility > System Evolution and Operation
Deposited By: Ravani Nanjundaswamy, Nithin
Deposited On:09 May 2023 15:03
Last Modified:24 Apr 2024 20:55

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