RISC-V Timing-Instructions for Open Time-Triggered Architectures

Abstract

Time-triggered architectures (TTAs) were a key enabler for time-predictable software execution and, thus, for cyber-physical and embedded systems with real-time requirements. Controlling software-execution by the means of timer-controlled interrupts and a predetermined schedule, TTAs are a common standard to ensure timing in safety-critical systems. Now, with the emerge of the openly available RISC-V architectures and the use of its instruction-set extension allows to easily provide softcore-processors with an application-specific instruction-set configuration. To support the realtime-capability of such RISC-V based, application-specific instruction-set processors (ASIPs), the presented approach provides timing-instructions as a RISC-V instruction-set extension to measure and control the software execution-time at the hardware-level.