A hybrid RISC-V architecture supporting mixed timing-critical and high performance workloads

Abstract

The hardware platforms available today for embedded systems are already capable of implementing different classes of applications. These can be real-time applications, in which compliance with given time limits must be guaranteed, and high-performance applications, in which the aim is to execute as many instructions as possible per unit of time. The goal of this work is to propose a hybrid hardware platform that is capable of executing the above two classes of applications without suffering from mutually negative timing predictability and execution time optimization requirements. This work presents a set of requirements for such a hybrid hardware platform for embedded systems. Based on these requirements, various existing platforms, ranging from high-performance embedded to fully time-predictable architectures, are analyzed and compared. Based on this analysis, a new hybrid architecture is proposed that can switch between a real-time and high-performance execution mode at runtime.