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An FPGA/MPSoC Based Low Latency Onboard SAR Processor

Breit, Helko and Mandapati, Srikantha and Balss, Ulrich (2021) An FPGA/MPSoC Based Low Latency Onboard SAR Processor. In: International Geoscience and Remote Sensing Symposium (IGARSS), pp. 5159-5162. IEEE. IGARSS 2021, 12. Jul. - 16. Jul. 2021, Brussels, Belgium - virtual. doi: 10.1109/IGARSS47720.2021.9553539.

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Official URL: https://ieeexplore.ieee.org/document/9553539

Abstract

This paper describes the concept and prototype implementation of a low latency spaceborne onboard Synthetic Aperture Radar (SAR) processor runing on a Multi-Processor-System-On-Chip (MPSoC) computing device combining an ARM processor and a Field-Programmable-Gate-Array (FPGA). The SAR processor is designed to generate SAR imagery from TerraSAR-X stripmap data for subsequent ship detection and sea state determination. Low latency data processing is a key development goal. Currently, a raw data block of 8k×32k samples, covering 375 km^2 to 500 km^2 , is focused on the hardware within 4 s. Together with an attached level-2 ship detection, wind, and sea state processor, running on the same device, a SAR data processing chain for generation of maritime alerts is formed. This chain is part of a larger prototype system being developed in the frame of the H2020 EO-ALERT project which further comprises an optical data chain, data compression/encryption, and scheduling on multiple reconfigurable MPSoC boards.

Item URL in elib:https://elib.dlr.de/146688/
Document Type:Conference or Workshop Item (Speech)
Title:An FPGA/MPSoC Based Low Latency Onboard SAR Processor
Authors:
AuthorsInstitution or Email of AuthorsAuthor's ORCID iD
Breit, HelkoHelko.Breit (at) dlr.dehttps://orcid.org/0000-0001-7865-3288
Mandapati, SrikanthaSrikantha.Mandapati (at) dlr.deUNSPECIFIED
Balss, UlrichUlrich.Balss (at) dlr.deUNSPECIFIED
Date:16 July 2021
Journal or Publication Title:International Geoscience and Remote Sensing Symposium (IGARSS)
Refereed publication:Yes
Open Access:Yes
Gold Open Access:No
In SCOPUS:Yes
In ISI Web of Science:No
DOI :10.1109/IGARSS47720.2021.9553539
Page Range:pp. 5159-5162
Editors:
EditorsEmailEditor's ORCID iD
UNSPECIFIEDIEEEUNSPECIFIED
Publisher:IEEE
Series Name:2021 IEEE International Geoscience and Remote Sensing Symposium IGARSS
Status:Published
Keywords:SAR, on-board processing, TerraSAR-X, FPGA, MPSoC, EO-ALERT
Event Title:IGARSS 2021
Event Location:Brussels, Belgium - virtual
Event Type:international Conference
Event Dates:12. Jul. - 16. Jul. 2021
Organizer:IEEE
HGF - Research field:Aeronautics, Space and Transport
HGF - Program:Space
HGF - Program Themes:Earth Observation
DLR - Research area:Raumfahrt
DLR - Program:R EO - Earth Observation
DLR - Research theme (Project):R - SAR methods
Location: Oberpfaffenhofen
Institutes and Institutions:Remote Sensing Technology Institute > SAR Signal Processing
Deposited By: Breit, Helko
Deposited On:03 Dec 2021 13:04
Last Modified:01 Aug 2022 03:00

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