Efficient Implementation of On-Chip Communication Optimized for SpaceWire Networks

Abstract

SpaceWire has been used successfully as commu- nication backbone implemented on Field Programmable Gate Arrays (FPGAs) in several robotic systems at the DLR. However, the growing number of available System-on-Chip (SoC) solutions with integrated programmable logic and the demand for efficient processing power in embedded systems require high speed On- Chip communication. Using SpaceWire as interconnection bus inside FPGAs has a major drawback compared to dedicated On-Chip bus systems. As it is not designed to exploit the wide parallelism of FPGAs, several On-Chip communication standards outperform SpaceWire in terms of bandwidth and resource costs. Examples are the AMBA AXI bus, the Avalon bus, CoreConnect or the Wishbone SoC Interconnection. In this work, the Wishbone standard is used to show, how an FPGA system connected to a SpaceWire network can benefit from a dedicated On-Chip bus. The architecture of the Wishbone standard allows an almost seamless integration into a SpaceWire network. Essential parts of SpaceWire, like package oriented communication or time- code distribution, can be mapped onto the Wishbone standard. A slim protocol is presented to allow accessing the On-Chip address space from the SpaceWire network and vice versa. It is also shown, that a heterogeneous On-Chip network consisting of SpaceWire and Wishbone occupies less resources on an FPGA than a similar network implemented with SpaceWire only. In the future, this approach can be used to integrate SoCs with built-in programmable logic into a SpaceWire network.