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Bare Metal Porting of Tasking Framework on a Xilinx Board

Gopal, Ashish (2016) Bare Metal Porting of Tasking Framework on a Xilinx Board. Masterarbeit, ISAE-SUPAERO, University of Toulouse.

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Kurzfassung

The Tasking Framework is DLR’s solution for distributed and parallel computation. In many aspects this can be considered similar to an Operating system which does not have any computation functions of its own. It provides access to the resources like CPU time for tasks which require processing. These tasks can be requests from any sensor to process its data which could be crucial in attitude control of a space craft. This particular framework is currently employed by DLR in many of their existing projects. Each of these projects has different hardware requirements and hence the platform on which the framework is implemented differs from project to project. In order to have some uniformity and to reduce the efforts for more such implementations, the entire framework is divided into an API and a hardware dependent layer. As part of this project the API is relatively unchanged. All the modifications and changes are to be made only in the hardware dependent layer. The objective of this internship is to achieve a bare metal implementation of this framework. In all the existing implementations there has always been an underlying operating system. In this case the operating system is inexistent. The idea is stemmed from the observations made regarding excessive usage of resources, undesired over heads etc. when an operating system is running. The hardware selected for this implementation is provided by Xilinx. The evaluation board is based on Xilinx’s popular Zynq architecture. It comes with two ARM cortex A9 based processors which forms the core of the processing system on the board. It also accommodates an FPGA block which can be configured for specific purposes and used as a third processor for sharing the workload. In this internship however the FPGA was not used. The FPGA is however mapped with a bitstream file generated using the Vivado software package to be able to access the other peripherals. The implementation was successfully carried out and SMP architecture is implemented for sharing the workload between the two available processors.

elib-URL des Eintrags:https://elib.dlr.de/110774/
Dokumentart:Hochschulschrift (Masterarbeit)
Titel:Bare Metal Porting of Tasking Framework on a Xilinx Board
Autoren:
AutorenInstitution oder E-Mail-AdresseAutoren-ORCID-iDORCID Put Code
Gopal, AshishAshish.Gopal (at) dlr.deNICHT SPEZIFIZIERTNICHT SPEZIFIZIERT
Datum:2016
Referierte Publikation:Nein
Open Access:Ja
Seitenanzahl:53
Status:veröffentlicht
Stichwörter:Bare metal, SMP, Parallel processing, multitasking.
Institution:ISAE-SUPAERO, University of Toulouse
HGF - Forschungsbereich:Luftfahrt, Raumfahrt und Verkehr
HGF - Programm:Raumfahrt
HGF - Programmthema:Technik für Raumfahrtsysteme
DLR - Schwerpunkt:Raumfahrt
DLR - Forschungsgebiet:R SY - Technik für Raumfahrtsysteme
DLR - Teilgebiet (Projekt, Vorhaben):R - Scosa Onboard Computing (alt)
Standort: Braunschweig
Institute & Einrichtungen:Institut für Simulations- und Softwaretechnik
Institut für Simulations- und Softwaretechnik > Software für Raumfahrtsysteme und interaktive Visualisierung
Hinterlegt von: Gopal, Ashish
Hinterlegt am:25 Jan 2017 13:52
Letzte Änderung:31 Jul 2019 20:08

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