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Bare Metal Porting of Tasking Framework on a Xilinx Board

Gopal, Ashish (2016) Bare Metal Porting of Tasking Framework on a Xilinx Board. Master's, ISAE-SUPAERO, University of Toulouse.

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Abstract

The Tasking Framework is DLR’s solution for distributed and parallel computation. In many aspects this can be considered similar to an Operating system which does not have any computation functions of its own. It provides access to the resources like CPU time for tasks which require processing. These tasks can be requests from any sensor to process its data which could be crucial in attitude control of a space craft. This particular framework is currently employed by DLR in many of their existing projects. Each of these projects has different hardware requirements and hence the platform on which the framework is implemented differs from project to project. In order to have some uniformity and to reduce the efforts for more such implementations, the entire framework is divided into an API and a hardware dependent layer. As part of this project the API is relatively unchanged. All the modifications and changes are to be made only in the hardware dependent layer. The objective of this internship is to achieve a bare metal implementation of this framework. In all the existing implementations there has always been an underlying operating system. In this case the operating system is inexistent. The idea is stemmed from the observations made regarding excessive usage of resources, undesired over heads etc. when an operating system is running. The hardware selected for this implementation is provided by Xilinx. The evaluation board is based on Xilinx’s popular Zynq architecture. It comes with two ARM cortex A9 based processors which forms the core of the processing system on the board. It also accommodates an FPGA block which can be configured for specific purposes and used as a third processor for sharing the workload. In this internship however the FPGA was not used. The FPGA is however mapped with a bitstream file generated using the Vivado software package to be able to access the other peripherals. The implementation was successfully carried out and SMP architecture is implemented for sharing the workload between the two available processors.

Item URL in elib:https://elib.dlr.de/110774/
Document Type:Thesis (Master's)
Title:Bare Metal Porting of Tasking Framework on a Xilinx Board
Authors:
AuthorsInstitution or Email of AuthorsAuthors ORCID iD
Gopal, AshishAshish.Gopal (at) dlr.deUNSPECIFIED
Date:2016
Refereed publication:No
Open Access:Yes
Gold Open Access:No
In SCOPUS:No
In ISI Web of Science:No
Number of Pages:53
Status:Published
Keywords:Bare metal, SMP, Parallel processing, multitasking.
Institution:ISAE-SUPAERO, University of Toulouse
HGF - Research field:Aeronautics, Space and Transport
HGF - Program:Space
HGF - Program Themes:Space Technology
DLR - Research area:Raumfahrt
DLR - Program:R SY - Technik für Raumfahrtsysteme
DLR - Research theme (Project):R - Scosa Onboard Computing
Location: Braunschweig
Institutes and Institutions:Institut of Simulation and Software Technology
Institut of Simulation and Software Technology > Software for Space Systems and Interactive Visualisation
Deposited By: Gopal, Ashish
Deposited On:25 Jan 2017 13:52
Last Modified:31 Jul 2019 20:08

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