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Debug automation for logic circuits under timing variations

Dehbashi, Mehdi and Fey, Görschwin (2013) Debug automation for logic circuits under timing variations. IEEE Design and Test, 30 (6), pp. 60-69. IEEE - Institute of Electrical and Electronics Engineers. DOI: 10.1109/MDAT.2013.2266393 ISSN 2168-2356

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Abstract

This paper presents a novel approach to automate speedpath debugging taking into account variations. The proposed technique is based on Boolean Satisfiability. The approach is based on converting the timing behavior of a circuit into the functional domain, inserting a variation logic into the model, and using a Boolean Satisfiability solver to extract failing speedpaths.

Item URL in elib:https://elib.dlr.de/93696/
Document Type:Article
Title:Debug automation for logic circuits under timing variations
Authors:
AuthorsInstitution or Email of AuthorsAuthors ORCID iD
Dehbashi, MehdiUNSPECIFIEDUNSPECIFIED
Fey, GörschwinUNSPECIFIEDUNSPECIFIED
Date:2013
Journal or Publication Title:IEEE Design and Test
Refereed publication:Yes
Open Access:No
Gold Open Access:No
In SCOPUS:Yes
In ISI Web of Science:Yes
Volume:30
DOI :10.1109/MDAT.2013.2266393
Page Range:pp. 60-69
Publisher:IEEE - Institute of Electrical and Electronics Engineers
ISSN:2168-2356
Status:Published
Keywords:automate speedpath debugging
HGF - Research field:Aeronautics, Space and Transport
HGF - Program:Space
HGF - Program Themes:Space Technology
DLR - Research area:Raumfahrt
DLR - Program:R SY - Technik für Raumfahrtsysteme
DLR - Research theme (Project):R - Core Avionics
Location: Bremen
Institutes and Institutions:Institute of Space Systems > Avionics Systems
Deposited By: Hoffmann, Jana Christin
Deposited On:08 Jan 2015 13:00
Last Modified:08 Mar 2018 18:37

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