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Debugging HDL designs based on functional equivalences with high-level specifications

Finder, Alexander and Witte, Jan-Philipp and Fey, Görschwin (2013) Debugging HDL designs based on functional equivalences with high-level specifications. IEEE Int’l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Karlovy Vary.

Full text not available from this repository.

Official URL: http://dx.doi.org/10.1109/DDECS.2013.6549789


Item URL in elib:https://elib.dlr.de/86958/
Document Type:Conference or Workshop Item (Speech)
Title:Debugging HDL designs based on functional equivalences with high-level specifications
Authors:
AuthorsInstitution or Email of AuthorsAuthors ORCID iD
Finder, AlexanderUNSPECIFIEDUNSPECIFIED
Witte, Jan-PhilippUNSPECIFIEDUNSPECIFIED
Fey, GörschwinUNSPECIFIEDUNSPECIFIED
Date:2013
Refereed publication:Yes
Open Access:No
Gold Open Access:No
In SCOPUS:No
In ISI Web of Science:No
Page Range:pp. 60-65
Status:Published
Keywords:Hardware-Entwurf, Systembeschreibung, Äquivalenzprüfung, Integrierte Schaltkreise
Event Title:IEEE Int’l Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Event Location:Karlovy Vary
Event Type:international Conference
HGF - Research field:Aeronautics, Space and Transport
HGF - Program:Space
HGF - Program Themes:Space Technology
DLR - Research area:Raumfahrt
DLR - Program:R SY - Technik für Raumfahrtsysteme
DLR - Research theme (Project):R - Core Avionics
Location: Bremen
Institutes and Institutions:Institute of Space Systems > Avionics Systems
Deposited By: Fey, Görschwin
Deposited On:08 Jan 2014 12:47
Last Modified:08 May 2014 23:30

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