elib
DLR-Header
DLR-Logo -> http://www.dlr.de
DLR Portal Home | Imprint | Privacy Policy | Contact | Deutsch
Fontsize: [-] Text [+]

On modeling and evaluation of logic circuits under timing variations

Dehbashi, Mehdi and Fey , Görschwin and Roy, Kaushik and Raghunathan, Anand (2012) On modeling and evaluation of logic circuits under timing variations. EUROMICRO Symposium on Digital System Design (DSD), Cesme, Izmir, Turkey. DOI: 10.1109/DSD.2012.91

This is the latest version of this item.

Full text not available from this repository.

Official URL: http://dx.doi.org/10.1109/DSD.2012.91


Item URL in elib:https://elib.dlr.de/84407/
Document Type:Conference or Workshop Item (Speech)
Title:On modeling and evaluation of logic circuits under timing variations
Authors:
AuthorsInstitution or Email of AuthorsAuthors ORCID iD
Dehbashi, MehdiUNSPECIFIEDUNSPECIFIED
Fey , GörschwinUNSPECIFIEDUNSPECIFIED
Roy, KaushikUNSPECIFIEDUNSPECIFIED
Raghunathan, AnandUNSPECIFIEDUNSPECIFIED
Date:2012
Refereed publication:Yes
Open Access:No
Gold Open Access:No
In SCOPUS:No
In ISI Web of Science:No
DOI :10.1109/DSD.2012.91
Page Range:pp. 479-486
Status:Published
Keywords:Post-silicon diagnosis, process variations, electronic design automation, EDA
Event Title:EUROMICRO Symposium on Digital System Design (DSD)
Event Location:Cesme, Izmir, Turkey
Event Type:international Conference
HGF - Research field:Aeronautics, Space and Transport (old)
HGF - Program:Space (old)
HGF - Program Themes:W - no assignment
DLR - Research area:Space
DLR - Program:W - no assignment
DLR - Research theme (Project):W - no assignment (old)
Location: Bremen
Institutes and Institutions:Institute of Space Systems > Avionics Systems
Deposited By: Fey, Görschwin
Deposited On:01 Oct 2013 12:46
Last Modified:04 Oct 2016 12:52

Available Versions of this Item

Repository Staff Only: item control page

Browse
Search
Help & Contact
Information
electronic library is running on EPrints 3.3.12
Copyright © 2008-2017 German Aerospace Center (DLR). All rights reserved.