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Dehbashi, Mehdi and Fey , Görschwin and Roy, Kaushik and Raghunathan, Anand (2012) On modeling and evaluation of logic circuits under timing variations. EUROMICRO Symposium on Digital System Design (DSD), 2012-09-05 - 2012-09-08, Cesme, Izmir, Turkey. doi: 10.1109/DSD.2012.91.
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Official URL: http://dx.doi.org/10.1109/DSD.2012.91
| Item URL in elib: | https://elib.dlr.de/84407/ | ||||||||||||||||||||
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| Document Type: | Conference or Workshop Item (Speech) | ||||||||||||||||||||
| Title: | On modeling and evaluation of logic circuits under timing variations | ||||||||||||||||||||
| Authors: |
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| Date: | 2012 | ||||||||||||||||||||
| Refereed publication: | Yes | ||||||||||||||||||||
| Open Access: | No | ||||||||||||||||||||
| Gold Open Access: | No | ||||||||||||||||||||
| In SCOPUS: | No | ||||||||||||||||||||
| In ISI Web of Science: | No | ||||||||||||||||||||
| DOI: | 10.1109/DSD.2012.91 | ||||||||||||||||||||
| Page Range: | pp. 479-486 | ||||||||||||||||||||
| Status: | Published | ||||||||||||||||||||
| Keywords: | Post-silicon diagnosis, process variations, electronic design automation, EDA | ||||||||||||||||||||
| Event Title: | EUROMICRO Symposium on Digital System Design (DSD) | ||||||||||||||||||||
| Event Location: | Cesme, Izmir, Turkey | ||||||||||||||||||||
| Event Type: | international Conference | ||||||||||||||||||||
| Event Start Date: | 5 September 2012 | ||||||||||||||||||||
| Event End Date: | 8 September 2012 | ||||||||||||||||||||
| HGF - Research field: | Aeronautics, Space and Transport (old) | ||||||||||||||||||||
| HGF - Program: | Space (old) | ||||||||||||||||||||
| HGF - Program Themes: | W - no assignment | ||||||||||||||||||||
| DLR - Research area: | Space | ||||||||||||||||||||
| DLR - Program: | W - no assignment | ||||||||||||||||||||
| DLR - Research theme (Project): | W - no assignment (old) | ||||||||||||||||||||
| Location: | Bremen | ||||||||||||||||||||
| Institutes and Institutions: | Institute of Space Systems > Avionics Systems | ||||||||||||||||||||
| Deposited By: | Fey, Görschwin | ||||||||||||||||||||
| Deposited On: | 01 Oct 2013 12:46 | ||||||||||||||||||||
| Last Modified: | 05 Jun 2024 08:11 |
Available Versions of this Item
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On modeling and evaluation of logic circuits under timing variations. (deposited 07 Feb 2013 12:19)
- On modeling and evaluation of logic circuits under timing variations. (deposited 01 Oct 2013 12:46) [Currently Displayed]
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