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Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder

Rossi, Daniele and Martin, Omana and Garrammone, Giuliano and Metra, Cecilia and Jas, Abhijit and Galivanche, Rajesh (2013) Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder. Journal of Electronic Testing. Springer. ISSN 0923-8174

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Abstract

We propose a low cost concurrent error detection strategy to improve the Reliability, Availability, Serviceability (RAS) of high performance microprocessors, by specifically targeting one of its most critical blocks (fromthe point of view of the microprocessor RAS), that is the control logic. By discovering codes that are inherently present within the control logic because of its performed functionality and verification needs (referred to as Control Logic Function-Inherent Codes), it allows to achieve concurrent error detection at very limited costs in terms of area, power consumption, impact on performance and design. Considering for instance the case of the instruction decoder of a public domain microprocessor, we will prove that our approach requires significantly lower area and power than traditional parity encoding, while providing higher concurrent error detection ability. Therefore, if adopted together with a system level (generally software implemented) recovery technique, our strategy constitutes a viable and successful approach to increase the microprocessor RAS, at very limited costs.

Item URL in elib:https://elib.dlr.de/82745/
Document Type:Article
Title:Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder
Authors:
AuthorsInstitution or Email of AuthorsAuthors ORCID iD
Rossi, DanieleUniversity of BolognaUNSPECIFIED
Martin, OmanaUniversity of BolognaUNSPECIFIED
Garrammone, GiulianoDLRUNSPECIFIED
Metra, CeciliaUniversity of BolognaUNSPECIFIED
Jas, Abhijit Intel CorporationUNSPECIFIED
Galivanche, RajeshIntel CorporationUNSPECIFIED
Date:March 2013
Journal or Publication Title:Journal of Electronic Testing
Refereed publication:Yes
Open Access:No
Gold Open Access:No
In SCOPUS:Yes
In ISI Web of Science:Yes
Publisher:Springer
ISSN:0923-8174
Status:Published
Keywords:High performance microprocessor ; Control logic ; Concurrent error detection ; RAS
HGF - Research field:Aeronautics, Space and Transport
HGF - Program:Space
HGF - Program Themes:Communication and Navigation
DLR - Research area:Raumfahrt
DLR - Program:R KN - Kommunikation und Navigation
DLR - Research theme (Project):R - Vorhaben Multimedia Satellitennetze
Location: Oberpfaffenhofen
Institutes and Institutions:Institute of Communication and Navigation > Satellite Networks
Deposited By: Garrammone, Giuliano
Deposited On:13 Jun 2013 09:01
Last Modified:13 Jun 2013 09:01

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