Implementation of a Quaternary Message Passing Low-Density Parity-Check Decoder

Abstract

We present a hardware implementation and evaluation of a quaternary message-passing (QMP) low-density paritycheck (LDPC) decoder. The design targets high-throughput applications, where routing complexity and energy efficiency are large challenges from an implementation perspective. A comparison of the QMP decoder to a state-of-the-art normalized min-sum (NMS) decoder using a 12 nm fin field-effect transistor (FinFET) technology node shows that the QMP decoder achieves a 14.1 % increase in throughput and a 178.5 % improvement in energy efficiency. However, this is at the cost of a 0.35 dB loss in error correction performance.