Extending Clang/LLVM with Custom Instructions using TableGen – An Experience Report

Abstract

The extensibility of the RISC-V ISA by adding instructions allows for the rapid creation of custom processor cores. For that reason, it must be assured that the software tooling for this hardware does not become a bottleneck in this process. In this paper, we address this by describing an approach for automatically augmenting a compiler from a description of the instruction set extension. Our approach is based on Clang/LLVM with the custom instructions (RISC-V ISA-extensions) being described in a domain-specific language (DSL) called CoreDSL. These CoreDSL definitions are automatically translated into corresponding Clang/LLVM updates (TableGen and C++) with the goal of avoiding invasive changes to the compiler, while enabling free use of the custom instructions. Despite various challenges we encountered in the process, we have successfully automated the modification of Clang/LLVM to support custom instructions throughout the whole software toolchain (compiler, linker and debugger) and present our leanings and proposed next steps to further apply our proposed concept in a stable tool environment. The presented concept is not limited to RISC-V cores, but could also be adopted for other platforms with custom instruction support.