Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core

Abstract

Optical Probing Attacks (OPA) have been shown as an effective solution to bypass several known protection schemes of integrated circuits and to read-out sensitive information, like security keys or Intellectual Property (IP). As countermeasure, we propose a method for designing high-performance OPA-hardened digital circuits. Several existing solutions for OPA-hardened designs require changes in the fabrication process, resulting in high cost increase. Other approaches suffer from notable performance reductions and require significant changes of the employed gate libraries. In this work, we alleviate these limitations and propose a methodology to design high-performance OPA-hardened circuits. We achieve this by using a two-step methodology. First, we design a high-performance, and Low optical Leakage Dual-Rail Logic (LoL-DRL) gate library based on a standard CMOS gate library. That means, no complete redesign of the layout required, unlike comparable approaches. Second, we propose a lightweight synthesis technique to synthesize OPA-hardened circuits from conventional circuits. Furthermore, we applied our methodology on a RISC-V core to design the first OPA-hardened RISC-V core named Lo-RISK. Our method ensures a negligible performance penalty, however at the notable costs in terms of area and power.