A RISC-V based platform supporting mixed timing-critical and high performance workloads

Abstract

Existing hardware platforms are typically optimized for either real-time or high-performance applications, which poses challenges when running a mix of both on the same platform. This work aims to address this issue by proposing a hybrid platform that can effectively execute both types of applications without compromising timing predictability or performance optimization. The proposed solution presents a hybrid HW/SW architecture template capable of dynamically switching between real-time and high-performance execution modes at runtime. The integration and implementation of this architecture template are described on an FPGA, utilizing an open-source RISC-V processor system and FreeRTOS as the software management layer. We have successfully applied the TACLe benchmark suite for the evaluation of our proposed approach. Through an integrated measurement infrastructure, the software functionality, execution timing, and switching times are analyzed on a single-core implementation of the proposed architecture template