Acceleration of an Autoencoder using a FPGA-SoC in a High-Performance Node of a Distributed Onboard Computer

Abstract

The thesis proposes the approach for calculating the activation functions of neural networks in the CPU while the linear matrix vector multiplication are calculated in a FPGA-accelerator. The approach is implemented on a Xilinx Zynq-7000 which provides a tight coupling between the CPU and FPGA. The system is running an embedded Linux operating system and the implementation is integrated into the ScOSA framework which is a designed for a distributed onboard computer of a satellite.