A DSL based approach for supporting custom RISC-V instruction extensions in LLVM

Abstract

The RISC-V ISA allows the definition of custom instruction extensions to support application specific hardware acceleration and optimization. The main challenge with instruction extensions is the time-consuming process of consistently integrating them within the processor design and the compiler support, and of provisioning a testing and evaluation framework for the software developer. Our work proposes an automatable customization of an LLVM compiler based on a DSL (Domain Specific Language) driven approach, which can already be used for the definition of the instruction extension, its integration into the RISC-V ISA, and the automatic synthesis of the processor core and an instruction set simulator. We demonstrate the whole generation flow on the example of a customized MAC instruction as a simple example and discuss the identified challenges.