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SAT-Hard: A Learning-based Hardware SAT-Solver

Ustaoglu, Buse and Huhn, Sebastian and Sill Torres, Frank and Große, Daniel and Drechsler, Rolf (2019) SAT-Hard: A Learning-based Hardware SAT-Solver. In: 22nd Euromicro Conference on Digital System Design, DSD 2019, pp. 71-81. IEEE. EUROMICRO Digital System Design Conference (DSD), Kallithea, Greece. doi: 10.1109/DSD.2019.00021.

Full text not available from this repository.

Official URL: https://ieeexplore.ieee.org/document/8875059

Abstract

Within the last decades, tremendous research work has been carried out on the development of software-based algorithms to solve the Boolean Satisfiability Problem. These SAT-solvers have then been heavily orchestrated for addressing complex computational tasks like the verification of circuits. In this field, most of the applied techniques focused only on the design phase of the circuit. Due to this fact, new approaches have been published in the literature solely focusing on online verification as well as self-verification. These kind of solutions strictly require Hardware (HW) SAT-solvers that can be integrated into a system while introducing only low hardware overhead and still providing high flexibility. By following these observations, this work presents SAT-Hard: In contrast to the state-of-the-art, SAT-Hard takes advantage of learning techniques to support features like clause learning and non-chronological backtracking, and combines them within a lightweight and standalone HW device. By this, a run-time speed-up of 2,000x can be achieved. Furthermore, the experimental evaluation clearly demonstrates that those complex problems can be solved in less than 20 seconds. Particularly due to its compactness, SAT-Hard is suitable for self-verification that enables the continuous verification of an integrated system during its lifetime.

Item URL in elib:https://elib.dlr.de/190670/
Document Type:Conference or Workshop Item (Speech)
Title:SAT-Hard: A Learning-based Hardware SAT-Solver
Authors:
AuthorsInstitution or Email of AuthorsAuthor's ORCID iD
Ustaoglu, BuseUniversität BremenUNSPECIFIED
Huhn, SebastianUNSPECIFIEDUNSPECIFIED
Sill Torres, FrankFrank.SillTorres (at) dlr.dehttps://orcid.org/0000-0002-4028-455X
Große, DanielUNSPECIFIEDUNSPECIFIED
Drechsler, RolfUniversität BremenUNSPECIFIED
Date:2019
Journal or Publication Title:22nd Euromicro Conference on Digital System Design, DSD 2019
Refereed publication:Yes
Open Access:No
Gold Open Access:No
In SCOPUS:Yes
In ISI Web of Science:No
DOI:10.1109/DSD.2019.00021
Page Range:pp. 71-81
Publisher:IEEE
Status:Published
Keywords:Hardware SAT-Solver, online-verification, IC design
Event Title:EUROMICRO Digital System Design Conference (DSD)
Event Location:Kallithea, Greece
Event Type:international Conference
HGF - Research field:other
HGF - Program:other
HGF - Program Themes:other
DLR - Research area:no assignment
DLR - Program:no assignment
DLR - Research theme (Project):no assignment
Location: Bremerhaven
Institutes and Institutions:Institute for the Protection of Maritime Infrastructures > Reslience of Maritime Systems
Deposited By: Sill Torres, Frank
Deposited On:24 Nov 2022 08:09
Last Modified:24 Nov 2022 08:09

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