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HAMBug: A Hybrid CPU-FPGA System to Detect Race Conditions

Damião Almeida, Danilo and Bragança, Lucas and Sill Torres, Frank and Ferreira, Ricardo and Nacif, José Augusto (2021) HAMBug: A Hybrid CPU-FPGA System to Detect Race Conditions. IEEE Transactions on Circuits and Systems II: Express Briefs, 68 (9), 3158 -3162. IEEE - Institute of Electrical and Electronics Engineers. doi: 10.1109/TCSII.2021.3093985. ISSN 1549-7747.

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Official URL: https://ieeexplore.ieee.org/document/9469913

Abstract

The evolution of computer algorithms and micro-architectures continuously leads to novel applications and solutions that explore modern computers potential. A drawback of this development is the rising complexity of hardware-oriented tests during software development. This brief proposes Hambug, a method to support developers during software testing of parallel applications in CPU-FPGA environments. The main component is a run-time memory analyzer that employs shared channels. Thus, Hambug enables memory analysis of parallel applications without influencing the CPU using a hardware-based debug module. Experimental results indicate that this method presents lower slowdown compared with modern dynamic analysis tools.

Item URL in elib:https://elib.dlr.de/143724/
Document Type:Article
Title:HAMBug: A Hybrid CPU-FPGA System to Detect Race Conditions
Authors:
AuthorsInstitution or Email of AuthorsAuthor's ORCID iD
Damião Almeida, DaniloUNSPECIFIEDUNSPECIFIED
Bragança, LucasUNSPECIFIEDUNSPECIFIED
Sill Torres, FrankFrank.SillTorres (at) dlr.dehttps://orcid.org/0000-0002-4028-455X
Ferreira, RicardoUNSPECIFIEDUNSPECIFIED
Nacif, José AugustoUNSPECIFIEDUNSPECIFIED
Date:1 July 2021
Journal or Publication Title:IEEE Transactions on Circuits and Systems II: Express Briefs
Refereed publication:Yes
Open Access:No
Gold Open Access:No
In SCOPUS:Yes
In ISI Web of Science:Yes
Volume:68
DOI :10.1109/TCSII.2021.3093985
Page Range:3158 -3162
Publisher:IEEE - Institute of Electrical and Electronics Engineers
ISSN:1549-7747
Status:Published
Keywords:Parallel computing FPGA heterogeneous architectures software validation
HGF - Research field:other
HGF - Program:other
HGF - Program Themes:other
DLR - Research area:no assignment
DLR - Program:no assignment
DLR - Research theme (Project):no assignment
Location: Bremerhaven
Institutes and Institutions:Institute for the Protection of Maritime Infrastructures > Reslience of Maritime Systems
Deposited By: Sill Torres, Frank
Deposited On:13 Sep 2021 13:02
Last Modified:13 Sep 2021 13:02

Available Versions of this Item

  • HAMBug: A Hybrid CPU-FPGA System to Detect Race Conditions. (deposited 13 Sep 2021 13:02) [Currently Displayed]

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