Evaluation of interface options for transmitting data to hardware accelerators on a Xilinx Zynq architecture

Abstract

FPGAs increasingly appear as tailorable hardware support for main processors. Their reprogrammability makes them are more dynamic than dedicated ASIC-hardware, but suffers from (more) overhead in communication costs. The coordination between an accelerator and the connected software is one of the main factors in these costs. In fact, there are scenarios in which the communication-overhead of using a FPGA-coprocessor may outweight the speed gain. This paper tries to understand the performance limits of an FPGA-accelerator, by measuring calculation speeds with varying sizes of data and over different driver implementations. It studies factors ofsoftware/driver architecture and communication overhead under a real application, using Embedded linux and a Software-Tasking-Framework developed by the german aerospace center (DLR). The goal here, is to identify performance relevant design decision, as well as limits in performance