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An Efficient NB-LDPC Decoder Architecture for Space Telecommand Links

Álvarez, Ángel and Fernández, Víctor and Matuz, Balazs (2020) An Efficient NB-LDPC Decoder Architecture for Space Telecommand Links. IEEE Transactions on Circuits and Systems II: Express Briefs. IEEE - Institute of Electrical and Electronics Engineers. doi: 10.1109/TCSII.2020.3034392. ISSN 1549-7747.

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Abstract

In the frame of error correction in space telecommand (TC) links, the Consultative Committee for Space Data Systems (CCSDS) currently recommends short block-length BCH and binary LDPC codes. Other alternatives have been discarded due to their high decoding complexity, such as LDPC and eBCH codes with MRB decoding and NB-LDPC codes. NBLDPC codes perform better than their binary counterparts over AWGN and jamming channels, being excellent candidates for space communications. In this brief, we show the feasibility of NB-LDPC coding for space TC applications by proposing a highly efficient decoding architecture. The proposed decoder is implemented for a (128,64) NB-LDPC code over GF(16) and the design is particularized for a space-certified Virtex-5QV FPGA. The results prove that NB-LDPC coding is an alternative outperforming the standardized binary LDPC at a reasonable cost. Given that the maximum rate for TC recommended by the CCSDS is 2 Mbps, the proposed architecture achieves a throughput of 2.4 Mbps using only 8797 LUTs and 5460 FFs (no dedicated memories are used). In addition, this architecture is suitable for any regular (2,4) NB-LDPC (128,64) code over GF(16) independently of the H matrix, allowing great flexibility for the use with the recently proposed short block-length NBLDPC codes in upcoming telecommand uplink standards.

Item URL in elib:https://elib.dlr.de/139390/
Document Type:Article
Title:An Efficient NB-LDPC Decoder Architecture for Space Telecommand Links
Authors:
AuthorsInstitution or Email of AuthorsAuthor's ORCID iDORCID Put Code
Álvarez, Ángelalvarez (at) teisa.unican.esUNSPECIFIEDUNSPECIFIED
Fernández, Víctorvictor (at) teisa.unican.esUNSPECIFIEDUNSPECIFIED
Matuz, BalazsBalazs.Matuz (at) dlr.dehttps://orcid.org/0000-0002-0133-6564UNSPECIFIED
Date:October 2020
Journal or Publication Title:IEEE Transactions on Circuits and Systems II: Express Briefs
Refereed publication:Yes
Open Access:Yes
Gold Open Access:No
In SCOPUS:Yes
In ISI Web of Science:Yes
DOI:10.1109/TCSII.2020.3034392
Publisher:IEEE - Institute of Electrical and Electronics Engineers
ISSN:1549-7747
Status:Published
Keywords:VLSI design, FPGA, non-binary LDPC codes, decoder architecture, space communication.
HGF - Research field:Aeronautics, Space and Transport
HGF - Program:Space
HGF - Program Themes:Communication and Navigation
DLR - Research area:Raumfahrt
DLR - Program:R KN - Kommunikation und Navigation
DLR - Research theme (Project):R - Vorhaben Multimedia Satellitennetze (old)
Location: Oberpfaffenhofen
Institutes and Institutions:Institute of Communication and Navigation > Satellite Networks
Deposited By: Matuz, Balazs
Deposited On:09 Dec 2020 15:10
Last Modified:28 Mar 2023 23:58

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