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Volatile Register Handling for FPGA Verification Based on SVAs Incorporated into UVM Environments

Borchers, Kai and Montenegro, Sergio and Dannemann, Frank (2019) Volatile Register Handling for FPGA Verification Based on SVAs Incorporated into UVM Environments. In: IEEE Aerospace Conference Proceedings. IEEE Aerospace Conference, USA. doi: 10.1109/AERO.2019.8742109.

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Abstract

Verification of Field Programmable Gate Array (FPGA) designs is a challenging task which can be managed in different ways. By now, Universal Verification Methodology (UVM) is the de-facto standard for functional verification of Register Transfer Level (RTL) designs throughout all industry branches. Among others, UVM proposes to check for correct Device Under Test (DUT) behavior in an automated way, based on observing applied stimulus used to predict the expected DUT reaction. However, the prediction requires a DUT model whereas some DUT properties are complicated or even impossible to predict. Volatile registers are an example for this kind of problem. This paper introduces a way to incorporate volatile register comparisons inside the UVM environment alongside standard registers. This is done by utilizing SystemVerilog Assertions (SVA) which observe volatile registers to provide their values to the UVM environment directly at the time they are accessed.

Item URL in elib:https://elib.dlr.de/131487/
Document Type:Conference or Workshop Item (Speech)
Title:Volatile Register Handling for FPGA Verification Based on SVAs Incorporated into UVM Environments
Authors:
AuthorsInstitution or Email of AuthorsAuthor's ORCID iDORCID Put Code
Borchers, KaiUNSPECIFIEDUNSPECIFIEDUNSPECIFIED
Montenegro, SergioUNSPECIFIEDUNSPECIFIEDUNSPECIFIED
Dannemann, FrankUNSPECIFIEDhttps://orcid.org/0000-0002-0636-5866138661081
Date:March 2019
Journal or Publication Title:IEEE Aerospace Conference Proceedings
Refereed publication:Yes
Open Access:No
Gold Open Access:No
In SCOPUS:Yes
In ISI Web of Science:No
DOI:10.1109/AERO.2019.8742109
Status:Published
Keywords:UVM, SVA, FPGA
Event Title:IEEE Aerospace Conference
Event Location:USA
Event Type:international Conference
HGF - Research field:Aeronautics, Space and Transport
HGF - Program:Space
HGF - Program Themes:Space System Technology
DLR - Research area:Raumfahrt
DLR - Program:R SY - Space System Technology
DLR - Research theme (Project):R - Scosa Onboard Computing (old)
Location: Bremen
Institutes and Institutions:Institute of Space Systems > Avionics Systems
Deposited By: Borchers, Kai
Deposited On:28 Nov 2019 10:48
Last Modified:25 Jul 2023 07:59

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