Analyzing an SET at Gate Level using a Conservative Approach

Abstract

Due to the decreasing size of transistors, the probability of transient errors and the variability of the transistor’s characteristics in electrical circuits continues increasing. These issues demand for techniques to check the robustness of circuits and their behavior under transient errors and conservative variability approximations. We present a conservative algorithm to decide if a transient error leads to faulty output of a circuit. Our approach considers logical, timing, and electrical masking as well as variability in the gates. We model these aspects and transient errors at the gate-level ensuring conservativeness of our analysis. In experiments, we compare our algorithm to precise spice-simulations and show the runtime of our implementation on the ISCAS-85 benchmarks.