elib
DLR-Header
DLR-Logo -> http://www.dlr.de
DLR Portal Home | Imprint | Privacy Policy | Contact | Deutsch
Fontsize: [-] Text [+]

Exploiting error detection latency for parity-based soft error detection

Aydos, Gökce and Fey, Görschwin (2016) Exploiting error detection latency for parity-based soft error detection. In: IEEE International Test Conference (TC), pp. 1-6. IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), 20.-22. April 2016, Kosice, Slowakei. doi: 10.1109/DDECS.2016.7482440. ISBN 978-1-5090-2467-4.

[img] PDF - Only accessible within DLR
249kB

Official URL: http://ieeexplore.ieee.org/document/7482440/

Abstract

Local triple modular redundancy (LTMR) is often the first choice to harden a flash-based FPGA application against soft errors in space. Unfortunately, LTMR leads to at least 300% area overhead. We propose a parity-based error detection approach, to use the limited resources of space-proven flash-based FPGAs more area-efficiently; this method can be the key for fitting the application onto the FPGA. A drawback of parity-based hardening is the significant impact on the critical path. To alleviate this error detection latency, pipeline structures in the design can be utilized. According to our results, this eliminates from 22% to 65% of the critical path overhead of the unpipelined error detection. Compared with LTMR, the new approach increases the critical path overhead of LTMR by a factor varying from 2 to 7.

Item URL in elib:https://elib.dlr.de/105827/
Document Type:Conference or Workshop Item (Speech)
Title:Exploiting error detection latency for parity-based soft error detection
Authors:
AuthorsInstitution or Email of AuthorsAuthor's ORCID iD
Aydos, GökceUNSPECIFIEDUNSPECIFIED
Fey, GörschwinUNSPECIFIEDUNSPECIFIED
Date:2016
Journal or Publication Title:IEEE International Test Conference (TC)
Refereed publication:Yes
Open Access:No
Gold Open Access:No
In SCOPUS:Yes
In ISI Web of Science:No
DOI :10.1109/DDECS.2016.7482440
Page Range:pp. 1-6
ISBN:978-1-5090-2467-4
Status:Published
Keywords:Field programmable gate arrays, Redundancy, Software, Computer architecture, Aerospace electronics, Data handling, Pipelines, reliability, Cross-Level Fault Handling
Event Title:IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Event Location:Kosice, Slowakei
Event Type:international Conference
Event Dates:20.-22. April 2016
HGF - Research field:Aeronautics, Space and Transport
HGF - Program:Space
HGF - Program Themes:Space System Technology
DLR - Research area:Raumfahrt
DLR - Program:R SY - Space System Technology
DLR - Research theme (Project):R - Small Sat Kleinsatelliten (old), R - Systemtechnologien (old)
Location: Bremen
Institutes and Institutions:Institute of Space Systems > Avionics Systems
Deposited By: Mörz, Martina
Deposited On:25 Aug 2016 09:31
Last Modified:20 Jun 2021 15:47

Repository Staff Only: item control page

Browse
Search
Help & Contact
Information
electronic library is running on EPrints 3.3.12
Website and database design: Copyright © German Aerospace Center (DLR). All rights reserved.