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Connected Component Labeling algorithm for very complex and high-resolution images on an FPGA platform

Schwenk, Kurt and Huber, Felix (2015) Connected Component Labeling algorithm for very complex and high-resolution images on an FPGA platform. In: SPIE Proceedings 9646, High-Performance Computing in Remote Sensing V, 9646. SPIE. SPIE Remote Sensing. International Society for Optics and Photonics, 2015, 21.-24. Sep. 2015, Toulouse, Frankreich. doi: 10.1117/12.2194101.

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Official URL: http://dx.doi.org/10.1117/12.2194101


Connected Component Labeling (CCL) is a basic algorithm in image processing and an essential step in nearly every application dealing with object detection. It groups together pixels belonging to the same connected component (e.g. object). Special architectures such as ASICs, FPGAs and GPUs were utilised for achieving high data throughput, primarily for video processing. In this article, the FPGA implementation of a CCL method is presented, which was specially designed to process high resolution images with complex structure at high speed, generating a label mask. In general, CCL is a dynamic task and therefore not well suited for parallelisation, which is needed to achieve high processing speed with an FPGA. Facing this issue, most of the FPGA CCL implementations are restricted to low or medium resolution images (≤ 2048 ∗ 2048 pixels) with lower complexity, where the fastest implementations do not create a label mask. Instead, they extract object features like size and position directly, which can be realized with high performance and perfectly suits the need for many video applications. Since these restrictions are incompatible with the requirements to label high resolution images with highly complex structures and the need for generating a label mask, a new approach was required. The CCL method presented in this work is based on a two-pass CCL algorithm, which was modified with respect to low memory consumption and suitability for an FPGA implementation. Nevertheless, since not all parts of CCL can be parallelised, a stop-and-go high-performance pipeline processing CCL module was designed. The algorithm, the performance and the hardware requirements of a prototype implementation are presented. Furthermore, a clock-accurate runtime analysis is shown, which illustrates the dependency between processing speed and image complexity in detail. Finally, the performance of the FPGA implementation is compared with that of a software implementation on modern embedded platforms.

Item URL in elib:https://elib.dlr.de/100363/
Document Type:Conference or Workshop Item (Speech)
Title:Connected Component Labeling algorithm for very complex and high-resolution images on an FPGA platform
AuthorsInstitution or Email of AuthorsAuthor's ORCID iD
Schwenk, KurtKurt.Schwenk (at) dlr.deUNSPECIFIED
Huber, FelixFelix.Huber (at) dlr.deUNSPECIFIED
Date:21 September 2015
Journal or Publication Title:SPIE Proceedings 9646, High-Performance Computing in Remote Sensing V
Refereed publication:No
Open Access:Yes
Gold Open Access:No
In ISI Web of Science:No
DOI :10.1117/12.2194101
Series Name:SPIE Proceedings
Keywords:Connected Component Labeling, CCL, FPGA, on board, digital image processing, image processing
Event Title:SPIE Remote Sensing. International Society for Optics and Photonics, 2015
Event Location:Toulouse, Frankreich
Event Type:international Conference
Event Dates:21.-24. Sep. 2015
Organizer:SPIE – The international society for optics and photonics
HGF - Research field:Aeronautics, Space and Transport
HGF - Program:Space
HGF - Program Themes:other
DLR - Research area:Raumfahrt
DLR - Program:R - no assignment
DLR - Research theme (Project):R - no assignment
Location: Oberpfaffenhofen
Institutes and Institutions:Space Operations and Astronaut Training > Space Flight Technology
Deposited By: Schwenk, Kurt
Deposited On:07 Dec 2015 09:50
Last Modified:31 Jul 2019 19:57

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