elib
DLR-Header
DLR-Logo -> http://www.dlr.de
DLR Portal Home | Imprint | Contact | Deutsch
Fontsize: [-] Text [+]

On modeling and evaluation of logic circuits under timing variations

Dehbashi, Mehdi and Fey , Görschwin and Roy, Kaushik and Raghunathan, Anand (2012) On modeling and evaluation of logic circuits under timing variations. EUROMICRO Symposium on Digital System Design (DSD), Cesme, Izmir, Turkey.

This is the latest version of this item.

Full text not available from this repository.

Official URL: http://dx.doi.org/10.1109/DSD.2012.91


Document Type:Conference or Workshop Item (Speech)
Title:On modeling and evaluation of logic circuits under timing variations
Authors:
AuthorsInstitution or Email of Authors
Dehbashi, MehdiUNSPECIFIED
Fey , GörschwinUNSPECIFIED
Roy, KaushikUNSPECIFIED
Raghunathan, AnandUNSPECIFIED
Date:2012
Refereed publication:Yes
In ISI Web of Science:No
Status:Published
Keywords:Post-silicon diagnosis, process variations, electronic design automation, EDA
Event Title:EUROMICRO Symposium on Digital System Design (DSD)
Event Location:Cesme, Izmir, Turkey
Event Type:international Conference
HGF - Research field:Aeronautics, Space and Transport (old)
HGF - Program:Space (old)
HGF - Program Themes:W - no assignement
DLR - Research area:Space
DLR - Program:W - no assignement
DLR - Research theme (Project):W -- no assignement (old)
Location: Bremen
Institutes and Institutions:Institute of Space Systems > Avioniksysteme
Deposited By: Görschwin Fey
Deposited On:01 Oct 2013 12:46
Last Modified:01 Oct 2013 12:46

Available Versions of this Item

Repository Staff Only: item control page

Browse
Search
Help & Contact
Informationen
electronic library is running on EPrints 3.3.12
Copyright © 2008-2012 German Aerospace Center (DLR). All rights reserved.