Implementation of a RISC-V Multicore System for the Flight Control of a Helicopter

Kurzfassung

Flight controllers have been shown to improve the safety, stability, and performance of aircraft. Certification according to DO-178C of systems that control aircraft is very hard, as potential errors may lead to catastrophic results. Thus, implementations are designed conservatively, using redundant singlecore processors operating at modest clock rates. Advanced control strategies like model predictive control (MPC) show superior performance and allow for obstacle collision avoidance, but have higher performance requirements. This thesis proposes a multicore architecture with a strong focus on isolation and more novel interprocessor communication strategies in comparison to traditional symmetric multicore systems (FIFOs, replicated scratchpad memory, and a synchronization device) that guarantee constant memory access times. Easing certification in contrast to traditional symmetric multiprocessor systems, as it provides isolation, reduces nondeterminism, and improves worst-case execution time analysis. The architecture is implemented with FPGA technology, programmed with a flight controller, and evaluated via hardware in the loop (HIL) simulation. Furthermore, the thesis explores the scalability of the architecture, provides guidance on writing programs for this architecture, and offers an outlook on how modern control strategies can benefit from the proposed architecture.