elib
DLR-Header
DLR-Logo -> http://www.dlr.de
DLR Portal Home | Imprint | Privacy Policy | Accessibility | Contact | Deutsch
Fontsize: [-] Text [+]

Design and Implementation of a Memory-Efficient, On-Board Azimuth Interpolation Scheme for Staggered-SAR

Keskinkilic, Berkay (2026) Design and Implementation of a Memory-Efficient, On-Board Azimuth Interpolation Scheme for Staggered-SAR. Master's, Karlsruher Institut für Technologie (KIT).

Full text not available from this repository.


Item URL in elib:https://elib.dlr.de/220053/
Document Type:Thesis (Master's)
Title:Design and Implementation of a Memory-Efficient, On-Board Azimuth Interpolation Scheme for Staggered-SAR
Authors:
AuthorsInstitution or Email of AuthorsAuthor's ORCID iDORCID Put Code
Keskinkilic, Berkayberkay.keskinkilic (at) dlr.deUNSPECIFIEDUNSPECIFIED
DLR Supervisors:
ContributionDLR SupervisorInstitution or E-MailDLR Supervisor's ORCID iD
Thesis advisorMarten, Christianjohann.marten (at) dlr.dehttps://orcid.org/0009-0003-2093-8848
Date:2026
Open Access:No
Number of Pages:80
Status:Unpublished
Keywords:FPGA, Staggered-SAR, FIR Filter
Institution:Karlsruher Institut für Technologie (KIT)
Department:Institut für Technik der Informationsverarbeitung (ITIV)
HGF - Research field:Aeronautics, Space and Transport
HGF - Program:Space
HGF - Program Themes:Earth Observation
DLR - Research area:Raumfahrt
DLR - Program:R EO - Earth Observation
DLR - Research theme (Project):R - SAR methods
Location: Oberpfaffenhofen
Institutes and Institutions:Microwaves and Radar Institute > Radar Concepts
Deposited By: Marten, Christian
Deposited On:01 Dec 2025 16:28
Last Modified:27 Jul 2026 09:59

Repository Staff Only: item control page

Browse
Search
Help & Contact
Information
OpenAIRE Validator logo electronic library is running on EPrints
Website and database design: Copyright © German Aerospace Center (DLR). All rights reserved.